Previously, a NAND-type memory device has been used as a nonvolatile semiconductor memory device. The NAND-type memory device includes a plurality of divided line-shaped portions in an upper layer portion of a silicon substrate, and the line-shaped portions are used as active areas. Multiple memory cells are formed in respective active areas, and a pair of selection gate electrodes are provided on both sides of the multiple memory cells. Moreover, a bit line and a source line are provided above the silicon substrate, and are connected to both sides of the pair of the selection gate electrodes. Here, at least the bit line is connected to the active area via a contact.
However, advanced shrinking of the NAND-type memory device causes reduction of margin for short circuit between adjacent contacts. More specifically, shift of a position of contact due to fluctuation of a manufacturing process may cause a problem of short-circuit between two contacts connected to adjacent active areas. Hence, a technique (for example, refer to FIG. 1 in JP-A 2009-54941 (Kokai)) has been proposed, in which contacts are arranged in a zigzag alignment as viewed from above.
However, although the margin for short circuit between the contacts can be improved by arranging the contacts in the zigzag alignment, the margin for short circuit between the contact and the active area cannot be improved. More specifically, on reduction of a spacing between active areas, short circuit badly occurs between a contact connected to a certain active area and another active area disposed next to the active area. Therefore, shrinking of the NAND-type memory device causes to reduce a yield of products.